Due to the sending principle of OV7670 is similar to the VGA display port, hence, the display protocol was selected as the display protocol.
Before the implementation of VGA display, the pixel data should be firstly stored in a dual RAM and VGA display module can read data from dual RAM. Two parts have independent clock signal, hence the clock sequence between VGA display and OV7670 can be combined together without error of address and clock.
To complete this function, IP core can be directly applied in this part.
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| Figure 1. IP core of dual RAM |
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| Figure 2. Basic Timing Diagram of VGA display [1] |
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| Figure 3. VGA Timing Specification [1] |
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| Figure 4. Parameters of VGA Timing |
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| Figure 5. IP core of convertor from VGA to HDMI |
Reference:
[1] S.Larson, "VGA Controller", Mar 07, 2018 [Online]. Available: https://www.digikey.com/eewiki/pages/viewpage.action?pageId=15925278





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