This week is the first week of this project. The achievement of this week is completed the configuration of the camera registers and the PMOD inputs ports.

Actually, the PMOD inputs ports configuration is gathered from Github contributions [1] and the official documents [2]. Moreover, the configuration of registers is obtained from website [3].
In this part, the configuration of OV7670 was completed with Serial Camera Control Bus (SCCB) or I2C serial communication protocol. Moreover, due to the FPGA board only has HDMI display port and the adaptor may disable the signal transmission, the conversion of VGA signal to HDMI signal should be done inside of the board. These two parts will be explained in the following contents.

1. SCCB/ I2C Data Bus [1]:

Actually, these two protocols are similar even some programmers just consider these two as a single stuff. Hence, the SCCB protocol was applied in this project and this will be explained precisely.
SCCB is a simple bidirectional communication protocol for low-speed devices, for instance, OV7670 camera module. This standard uses a controller called master device to communicate with slave devices and the slave can only transmit data if master has already addressed this slave. In the physical compositions, SCCB consist of serial clock (SIO_C) and serial data (SIO_D) lines to complete the communication functions. To complete the communication process, several important points should be emphasized.

• START and STOP signals

Figure 1. The example of START signal, the front straight line

• Each phase has 8 bits data and the end of each phase is Don't-Care bit

Figure 2. Composition of each phase

• 3-phase data transmit ID Address (Slave address), Sub-Address (Register location), Write Data (Overwrite content)

Figure 3. Composition of 3-phase transmission cycle

• The 9th bit, D0 defines write or read operation, this can be seen in Figure 1.

According to these instructions, the required waveform of to configure the OV7670 module can be derived. From the instruction, these 3-phase signals can be separated as 32 bits data and the SIO_C should be divided into 4 parts to create the positive edges and negative edges. Furthermore, the START signal is obtained when the SIO_C is high and SIO_D changed from high to low. The STOP signal is the same behavior, however, the SIO_D is changing from low to high when the SIO_C is high.

Figure 4. Total 3-phase signal

Moreover, according to the actual data of OV7670, the required clock frequency can also be obtained. Single bit transmission cycle time has a minimum 10 us requirement. Hence, the frequency of changing data bit should be lower than 100 kHz. Due to the frequency provided by the FPGA board is 100MHz, the required clock should be delayed, and 11 bits counter could provide 100M/2047 Hz. The delayed clock signal can be obtained from a 20 bits counter (Lower 11 bits for delay and higher bits for the counter of SIO_D).

Figure 5. Electrical characteristics of OV7670

Finally, the required waveform of configuration can be achieved. There are two different methods to get this result, the first one is using 'case' syntax and another one is using a shift register to output the SIO_D. The shift register was applied because the simplicity of this way. In this part, the SIOD_EN is an enable signal to stop the SIO_D output when the Don't-Care bits is input from OV7670.

Figure 6. The implementation of this shift register

Figure 7. Plot the SIO_C and set the SIOD_EN signal

According to the simulation waveform, the actual configuration has been achieved. First 32 bits are 0x01, 0x02, 0x03 and the second bits are 0x01, 0x55, 0xaa.

Figure 8. The simulation result of SCCB protocol

Reference:

[1] Omnivision, "Serial Camera Control Bus Functional Specification" , 2002, [Online]. Available: http://www4.cs.umanitoba.ca/~jacky/Teaching/Courses/74.795-LocalVision/ReadingList/ov-sccb.pdf